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VP216
Dual 90MHz 6-Bit Analog to Digital Converter with VCO Preliminary Information
DS4070 - 1.6 May 1996
The VP216 is a dual 90MHz 6-bit Analog to Digital Converter designed for use in consumer satellite receivers and decoders, video systems, multimedia and communications applications. Operating from a single +5V supply, the VP216 includes an on-chip high bandwidth ADC driver amplifier, a 6-bit ADC, VCO or Ext. clock interface. The VP216 also has the necessary bias voltages for the reference resistor chain in the 'flash' architecture of the ADC.
FEATURES s 90MHz Conversion Rate s VCO or Ext. Clock Interface s High Bandwidth ADC Driver Amplifier s Internal ADC Reference s TTL Data Outputs s Single 5 Volt Supply s Dual ADC System for good channel matching APPLICATIONS s Satellite Decoders s Multimedia s Communications ORDERING INFORMATION
VP216A CG HP1S (Commercial - 44 pin PLCC)
VRM 7 VRB 8 AVCC2 9 AGND2 10 COMP_I 11 AIN_I 12 AGND3 13 AVCC3 14 COMP_Q 15 AIN_Q 16 AGND4 17
39 DI2 38 DI1 37 DI0 36 DVCC 35 DGND 34 DQ5 33 DQ4 32 DQ3 31 DQ2 30 DQ1 29 DQ0
HP44
Fig.1 Pin connections - top view
------------------------------------------------9,14,18,23 1,2 36 COMP_I AIN_I 11 12 ADC DRIVER
AVCC
AVCC
DVCC
+
6-BIT ADC
VRB VRM VRT
6
LATCHES DATA OUTPUTS
VRM
7
37 38 39 40 41 42 CLOCK BUFFER VCO & XTAL OSC. 27 25 21 20 19 22
DI0 DI1 DI2 DI3 DI4 DI5 CLKOUT CLKIN TANK BIAS AGC CLKSEL DQ0 DQ1 DQ2 DQ3 DQ4 DQ5
VRB
8 VREF
OP AMPS
CLOCK DRIVER
CLK SEL
VRT AIN_Q COMP_Q
VRB VRM VRT
6 16 15 10,13,17,24 3,4
+
ADC DRIVER
6-BIT ADC
6
LATCHES DATA OUTPUTS
29 30 31 32 33 34
------------------------------------------------AGND AGND DGND
35
Fig.2 System block diagram
VP216
ABSOLUTE MAXIMUM RATINGS
DC supply voltage (VCC) -0.3 to +7V Analog input voltage (AIN) -0.3 to VCC+0.3V Digital inputs (CLKSEL, MSBSEL) VCC Digital output current (Ioh, Iol, Isc) -20 to +20mA Ambient operating temperature (Tamb) 0C to +70C Storage temperature (Tstorage) -55C to +125C
THERMAL CHARACTERISTICS
THERMAL RESISTANCES Junction to case(jc) Junction to ambient(jA) 19C/W 55C/W
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated) Tamb = 25C, AVCC = DVCC = +5V, full temperature range = 0C to +70C DC CHARACTERISTICS All specifications apply to either of the two ADCs Characteristic Resolution Static performance Differential non-linearity Integral non-linearity Missing codes Power supply Analog supply voltage Digital supply voltage Analog supply current Digital supply current Power dissipation Analog input Input range Input resistance Input capacitance Gain matching Input -3dB bandwidth Ain input voltage Comp output CLKIN Input voltage high Input voltage low Input current high Input current low TTL digital outputs Output voltage high Output voltage low Output current high Output current low AVCC DVCC AICC DICC P Symbol DNL INL Temp. +25C Full +25C Full Full Full Full +25C Full +25C Full +25C Full Full +25C +25C +25C +25C +25C +25C +25C Full +25C Full +25C Full +25C Full +25C Full +25C Full +25C Full +25C Full Test Level 4 4 4 4 4 4 4 1 4 1 4 1 4 5 1 5 1 4 1 1 1 4 1 4 1 4 1 4 1 4 1 4 1 4 1 4 4.75 4.75 60 15 375 4.5k 3.6 1.6 2.0 -0.2 2.4 Min. 6 Value Typ. Guaranteed 5.0 5.0 72 23 475 1.0 5.75k 3.0 200 3.85 1.8 5.25 5.25 85 30 575 7.5k 0.25 4.1 2.0 0.8 1 -0.5 3.0 0.4 -400 1 V V mA mA mA mA mW mW V pF dB MHz V V V V V V A mA Pk to Pk Max. 0.5 0.5 0.5 0.5 Units Bits LSB LSB LSB LSB Conditions
Vin Rin Cin AVH F3dB Aindc Vcomp Vih Vil Iih Iil
DVCC= 5.25V Vin = 2.7V DVCC= 5.25V Vin = 0.4V DVCC = 4.75V Ioh = -400A DVCC = 4.75V Iol = 1mA DVCC = 4.75V DVCC = 4.75V
Voh Vol Ioh Iol
V V V V A mA -
2
VP216
DC CHARACTERISTICS (cont.) Characteristic CLKSEL Input voltage high Input voltage low Input current high Input current low VCO Input capacitance Bias voltage AGC voltage Reference voltage REF 2.5 REF 3.0 REF 3.5 AC CHARACTERISTICS Characteristic Switching performance Clock high pulse width Clock low pulse width Max. conversion rate Data setup time Data hold time Aperture delay Aperture delay matching Aperture jitter Dynamic performance Differential non-linearity Integral non-linearity Signal to noise ratio Total harmonic distortion Effective No. of bits Crosstalk rejection Input offset Error rate Symbol Temp. Test Level 4 4 1 4 4 4 4 4 1 1 1 4 1 5 1 5 Min. 30 30 90 8 2 2 10 -0.95 31.8 40 5.0 Value Typ. 50 50 10 4 3 0.2 25 5.5 50 0.5 10e-8 Max. 70 70 4 0.5 50 +1.2 1 1 Units Conditions Symbol Temp. Test Level 1 4 1 4 1 4 1 4 5 1 1 1 1 1 Min. 2.0 -50 1.4 1.3 2.374 2.848 3.323 Value Typ. -100 2.0 1.6 1.65 2.525 3.03 3.55 Max. 0.8 1.0 -150 1.8 1.7 2.677 3.212 3.747 Units Conditions
Vih Vil Iih Iil
+25C Full +25C Full +25C Full +25C Full +25C +25C +25C +25C +25C +25C
V V V V A A
DVCC = 5.25V Vih = 2.7V DVCC = 5.25V Vil = 0.4V
Ctank Vbias Vagc VRB VRM VRT
pF V V V V V
}
no load
Tpw1 Tpw0 Fmax Tsu Th Tad Tad Taj DNL INL SNR THD ENOB CTR Vos BER
+25C +25C +25C Full Full +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C
% % MHz ns ns ns ns ps rms LSB LSB dB dBc bits dBc LSB
Cload=10pF Cload=10pF
AIN=15MHz AIN=15MHz
AIN=15MHz AIN=15MHz
NOTES 1. An input voltage of 0.0 volts 0.5 LSB should nominally correspond to the `011111' to `100000'B transition edge.
TEST LEVELS
Level 1 - 100% production tested. Level 2 - 100% production tested at 25C and sample tested at specified temperatures. Level 3 - Sample tested only. Level 4 - Parameter is guaranteed by design and characterisation testing. Level 5 - Parameter is typical value only.
3
VP216
PIN DESCRIPTIONS - 44 Pin J-lead PLCC package
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name AVCC 1 AVCC 1 AGND1 AGND1 AGND1 VRT VRM VRB AVCC2 AGND2 COMP-I AIN-I AGND3 AVCC3 COMP-Q AIN-Q AGND4 AVCC4 AGC BIAS TANK CLKSEL AVCC5 AGND5 CLKIN N.C. CLKOUT N.C. DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DGND DVCC DI0 DI1 DI2 DI3 DI4 DI5 N.C. N.C. Description Analog voltage supply for the 6-bit ADCs Analog voltage supply for the 6-bit ADCs Analog ground Analog ground Analog ground 3.5V reference voltage - ladder top Reference voltage - ladder middle 2.5V reference voltage - ladder bottom Analog voltage supply for the reference bias circuits Analog ground Capacitor compensation - I channel Analog signal input - I channel Analog ground for the I channel buffer amplifier Analog voltage supply for the I channel buffer amplifier Capacitor compensation - Q channel Analog signal input - Q channel Analog ground Analog voltage supply for the Q channel buffer amplifier AGC control voltage Input bias voltage Tank circuit connection Clock select - VCO or external clock Analog voltage supply for the VCO Analog ground Clock input positive Not connected Clock output positive Not connected Digital TTL output - LSB -Q channel
Digital TTL output - MSB - Q channel Digital ground Digital voltage supply Digital TTL output - LSB - I channel
Digital TTL output - MSB - I channel Not connected Not connected Table 1: Pin descriptions
4
An on-chip bandgap voltage reference circuit combined with two op amps provide all the necessary bias voltages
VP216
Device Description
The VP216 is a dual 90MHz 6-bit ADC system, (see Fig.2). Included on chip is a high bandwidth ADC driver amplifier, a 6-bit analog to digital converter, latches and TTL data outputs. The VP216 also has the necessary bias voltages for the reference resistor chain in the `flash' architecture of the ADC and has an optional VCO or external oscillator interface.
Clock Interface
The VP216 clock interface allows the ADC to be clocked in a number of ways. With the CLKSEL pin tied low the on chip VCO is selected. With the CLKSEL pin tied high the external TTL clock input is selected. CLKSEL 1 0 Table 2 The clock signal to the ADC synchronizes the sampling, conversion and output stages of the device as shown in the timing diagram (see Fig.4). The output of the ADC driver amp is sampled when the comparator array is latched after a rising edge of the input clock. Latched data is then presented to the TTL data outputs and latched on the falling edge of the input clock. The clock interface also provides a TTL clock output on pin 27. This output is limited to driving capacitive loads of 10pF. Output buffers are recommended for loads in excess of 10pF. Clock Source External Clock VCO
Analog Input
The analog inputs, (AIN_I,Q) are A.C. coupled into the non-inverting ADC driver amplifiers, which provide the necessary bandwidth, gain, offset and low impedance required to drive the ADC. The amplifier has been designed so that an input of 0 volts will produce an output level equal to the voltage present at the middle of the ADC resistor chain, (VRM = 3V typ.). This is achieved by an internal feedback loop within each amplifier which compares the amplifier output with VRM, (see Fig.3). This voltage will produce a transition binary code of 011111 to 100000 at the output of the ADC.
VRM
INPUT SIGNAL CCEXT.
ADC DRIVER AMP TO ADC
Input Voltage Code 1 Volt Full Scale 16mV = 1LSB Least +Ve Valid Input q q q q q q q Most +Ve Valid Input Table 3: Output coding Binary
DC SHIFT
00
COMP_(Q,I)
000000 000001 q 011111 100000 100001 q 111110 111111
01
CCOMP EXT.
q 31
Fig.3 DC offset internal feedback loop.
32 33
Reference Voltage
An on chip band gap voltage reference circuit combined with two op-amps provides all the necessary bias voltages for the ADC reference resistor chain, (VRB), (VRM) and (VRT). VRB, VRM and VRT have been brought out to pins 8, 7 and 6 respectively and should be decoupled with 100nF capacitors close to the package pins.
q 62 63
Digital Interface
The TTL data output pins, (DI0-DI5) and (DQ0-DQ5) have been optimized to interface with devices in close proximity to the VP216 and are designed to provide satisfactory logic levels at speeds up to 90MHz into a fanout of one and a total load capacitance of 10pF. All data outputs should have approximately equivalent loading to ensure proper setup and hold timing. For capacitive loads in excess of 10pF, output buffers are recommended.
5
VP216
V ref. AIN_(Q,I)
Comparator
Latch
Output Buffer Data Out Output Buffer
C
L
Clock to ADC
CLKOUT
N-1
N
N+1
AIN_(Q,I) Tpw 1 CLKOUT Tpw 0
Data Outputs Th
N-1 Tsu
N
N+1
TTL Threshold
Fig.4 System timing diagram
ELECTRICAL CHARACTERISTICS DEFINITIONS
Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency, as determined by FFT analysis is reduced by 3dB. Aperture Delay The delay between the rising edge of the 90MHz clock signal and the instant the analog input signal is sampled. Aperture Jitter The sample to sample variation in aperture delay. Bit Error Rate (BER) The number of spurious code errors produced for any given input sinewave frequency at a given clock frequency. In this case it is the number of codes occurring outside the histogram cusp for a 1/2 FS sinewave. Data Outputs, Set-up and Hold Time Data output timings are measured from 2.4V and 0.4V to the 1.4V threshold on the rising edge of the output clock. Differential Non-linearity The deviation in any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) This is a measure of a device's dynamic performance and may be obtained from the SNR or from a sine wave curve test fit according to the following expressions: ENOB = SNR-1.76/6.02 or
ENOB = N-log2[rms error (actual)/rms error (ideal)] where N is the conversion resolution and the actual rms error is the deviation from an ideal sine wave, calculated from the converter outputs with a sine wave input. Integral Non-linearity (INL) The deviation of the centre of each code from a reference line which has been determined by a least squares curve fit. Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude to the rms value of `noise' which is defined as the sum of all other spectral components, including the harmonics, but excluding D.C. with a full-scale analog input signal.
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